EH 7500 Memory Man

The above photos of an original Memory Man with alternate graphics and an EH-7500 circuit board show pots with 1976 date codes.  (Originally found these pics at forum.effectsdatabase.com.)  The photos do not match the EH-7500 schematic, but do match the “BBD ECHO ISSUE A” schematic. The above EH-7500 schematic dated 1/25/78, so I assume it is an earlier design.  In the pictures, there are 4 DIP ICs: 2x 4558 dual op amps, like the schematic above has, and 2x EH1048 chips, which are really CA3094 OTAs in disguise.  There are also 5 transistors on board.  One of the OTAs is used as a noise gate because the long delay settings are quite noisy in this design. This noise-gate is the precursor to the “squelch” feature.

The schematic above matches very closely to the trace I did of a EH 1309 Memory Man.

Note the lack of a compander chip (NE570/571).  The EH 7810 also lacks a compander and has a BOOST input.

IC 1A is an input buffer and voltage amplifier.  Normal mode has a voltage gain of x2.  BOOST mode has a x3.5 boost for low frequencies (see the 220n as short) and a 4.5x boost for high frequencies (see the 2n2 cap as short).

IC 2B provides a summing point for the input and feedback paths, and acts as a “anti-aliasing filter.”

IC 1B provides low pass filtering of the delayed output.  This could be considered a “reconstruction filter.”

IC 2A is tucked away between BBD stages.  It inverts the delayed signal and provides a buffered bias voltage to the next BBD stage (perhaps saves a coupling cap doing this).  Presumably the inversion is set up to cancel the inversion caused by IC1B.